Archiving

  • 분류 전체보기 (62)
    • CPU ARCHITECTURE1 (30)
      • CPU (21)
      • DRAM (6)
      • NAND (3)
    • SoC Protocol (13)
      • AMBA (13)
      • FIFO (0)
    • Verilog HDL (18)
      • Basics (15)
      • FPGA (3)
  • 홈
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  • 방명록
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전체 글

  • 02. Testbench & DUT(Design under test) 2024.10.06
  • 01. Clock 생성하기 2024.10.06
  • 07. DRAM CMD FLOW 2024.10.02
  • 06. DRAM ROW Access(Activate) & COL Access(Write/Read) 2024.10.02
  • 05. DRAM Signals 2024.10.02
  • 04. DRAM Structure 2024.10.02
  • 03. DRAM Array 2024.10.02
  • 02. DRAM Write & Read 2024.10.02
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