FSM + Counter
- Core가 IDLE인지 확인합니다.
- i_run신호와 counting 할 숫자를 core에 전달합니다.
- DONE이 될때까지 기다립니다.
- Verilog Code
* https://github.com/Vamosssss/Basic/tree/main/07.%20FSM/02.%20FSM%20%2B%20Counter
FSM(Traffic Light)
- RED will go to YELLOW after 30 cycles.
- YELLOW will go to GREEN after 5 cycles.
- GREEN will go RED after 20 cycles.
- The light color will be output.
- Verilog Code
* https://github.com/Vamosssss/Basic/tree/main/07.%20FSM/03.%20FSM(Traffic%20Light)
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